Higher speed and longer life as well as miniaturization have been required for recent semiconductor devices.
Patent Document 1 proposes a MOS transistor having a source region, a drain region, and a channel region and capable of operating even at a clock frequency of 10 GHz or more by improving the flatness of a surface of the channel region.
Specifically, Patent Document 1 points out that the high-speed operation is accomplished by flattening the surface of the channel region so that the flatness becomes 0.3 nm or less in terms of peak-to-valley (peak to valley) in a range of a length of 2 nm in a direction from the source to the drain.